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fvult
New Contributor
New ContributorAsync FIFO size in AVMM interconnect
We connect multiple AvalonMM masters to the Arria V Avalon MM PCIe IP. Qsys automatically creates an appropiate AVMM interconnect which looks as follows: Two Avalon masters (called dma_writer ...
sstrell
Super Contributor
Super ContributorYou could manually add FIFOs instead of the ones chosen by PD and set them to whatever depth you need. That's probably the easiest thing to do.
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