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Altera_Forum
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11 years ago

Asserting DEV_CLRn during configuration

Hi, I would like to know if on Cyclone IV devices DEV_CLRn is held asserted during configuration and beyond the initialization phase if that will cause the registers to remain reset right out o...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Thanks for the info. The idea is to have some pins forced to hi-Z while reset is asserted; this would be coded into the design file. The problem I have with DEV_OE is that it removes the weak pull-ups when it's asserted and that would let other output pins float.