Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

asi output clock

I had a problem with the asi output clock. At the output rx_data_clk I've put a pll and i've connected it to the inpiut inclk0, but when i've compiled i got this error:

Error: Clock input port inclk[0] of PLL "pll_3:inst30|altpll:altpll_component|pll_3_altpll:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block

Info: Input port INCLK[0] of node "pll_3:inst30|altpll:altpll_component|pll_3_altpll:auto_generated|pll1" is not connected

What shpoud I do?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    You should probably try to rearrange your project and let the input of your PLL come from an external dedicated clock input.

    Cheers.

    OD