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Altera_Forum
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11 years ago

Arrow SoCKit FPGA-to-HPS SDRAM (f2h_sdram) Help Needed!

Hello All!

I've been visiting this forum daily and, for the most part, finding answers to my questions. However, I've finally gotten to a point in my project hat I have no idea what I'm doing!

As a precursor, you should know that I'm a young engineer and I really do have very little experience using Altera products and coding linux drivers. But that is why I'm here -- to learn!

Also, I've successfully followed a nice tutorial by Zhemao (?) for using the lightweight HPS-to-FPGA bridge to control FPGA I/O, but I now need to understand how to use HPS DDR3 memory and how to access the HPS memory from the FPGA. I have read through this (http://www.alteraforum.com/forum/showthread.php?t=45290)tutorial, but I am looking for something a bit more in depth (step-by-step) from start to finish, if you will. Just a simple example (as described below).

I don't like to sell myself short, but... I've seen several examples on this forum and I really do need a dumbed-down, step-by-step guide of creating a very simple design (Qsys/Linux driver). Perhaps a simple example of taking a push button output (an HPS button?), storing it in DDR3 memory, and turning on an FPGA led...? That way I can begin to understand both the device driver, the Qsys, the Quartus, and the pin-layout aspects of dealing with DDR3 and f2h_sdram (possibly with the address span extender). As mentioned, I am using the Arrow SoCKit -- it has the Cyclone V 5CSXFC6D6F31C8 SoC. Any and all help is needed! (Even if it is just pointing me to other posts that I've already read.)

Note: For those who are interested, here's my ultimate project goal that I need to accomplish once I understand how to utilize DDR3... Recieve streaming video over ethernet (at giga-bit rate) through the HPS and store in DDR3 SDRAM; read the stored video from the FPGA (f2h_sdram0?) and perform predefined video processing; push the processed data back to the HPS (f2h_sdram1?) where further processing will be performed (tracking, etc.). If any one has better design ideas, feel free to share (in a PM preferably).

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi christnp, I'm the very beginner of the part of FPGA-to-HPS communication, and it really puzzles me a lot. So I would follow your post to see if there's any hint for the question.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi christnp,

    I'm in the exact shoes you were in. Did you eventually find documentation showing how to write to the SDRAM from the FPGA and read it from the HPS?

    Help would be greatly appreciated.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    andrydood,

    Unfortunately, I ran out of time before I was able to figure out a solution. However, before I stopped working on the project I believe was playing around with the VIP demo which can be found here:

    http://rocketboards.org/foswiki/view/projects/sockitvideoipvipreferencedesign

    It is using a DMA from HPS to FPGA, so it is not what you are looking for; however, if I recall correctly, I had read a couple posts on here (or maybe from some tech notes from Altera) that ultimately steered me away from the FPGA-to-HPS SDRAM bridge. I don't recall exactly what it was, I apologize.

    Sorry I couldn't have been more help. Taz1984 might be able to provide more support?

    R/
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    --- Quote Start ---

    andrydood,

    Unfortunately, I ran out of time before I was able to figure out a solution. However, before I stopped working on the project I believe was playing around with the VIP demo which can be found here:

    http://rocketboards.org/foswiki/view/projects/sockitvideoipvipreferencedesign

    It is using a DMA from HPS to FPGA, so it is not what you are looking for; however, if I recall correctly, I had read a couple posts on here (or maybe from some tech notes from Altera) that ultimately steered me away from the FPGA-to-HPS SDRAM bridge. I don't recall exactly what it was, I apologize.

    Sorry I couldn't have been more help. Taz1984 might be able to provide more support?

    R/

    --- Quote End ---

    There are several posts on the board about this, so I recommend searching around the forum. Several people have had it work by using either the F2S of F2H bridges, but it does require memory management to make sure nothing will be overwritten. If writing to the SDRAM, it is necessary to reserve space in the RAM (check out Uboot options) or by doing it with a kernel-mode driver. There are also sveral design examples now:

    The best one: https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/writing_to_hps_memory

    https://cloud.altera.com/devstore/platform/14.0.0/datamover-design-example/
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    And it works well-- as long as the ports are out of reset, you can treat it like any other slave device. Just make sure to reserve memory.

    It probably also makes sense to set up a protection rule to restrict access from the bridge to a desired range, just in case.