ArriaV DDR3 controller simulation model doen't read

Hello everybody :)

I'm trying to simulate DDR3 controller IP for ArriaV.

The IP was generated by Quartus 12.1, and I'm using Altera Modelsim 10.1b for simulation.

I took the simulation model of the memory controller from _sim folder and connected it to the encrypted memory model supplied in the _example_design.

Simulation is running like it should and I'm getting cal_success and init_done from the controller.

After the status lines are up, I'm performing a write cycle and I see the data going to the memory.

Then I try to read the data back from the same address. I see the memory respond to read command and the data is transferred on the dq lines.

Unfortunate readdatavalid line never goes up and the data is never driven to readdata port.

I've ran the example design and the same is happening there, readdatavalid is always down and no data ever present on read dataport.

What am I missing? Is that a known problem?

Thank,

Igal.