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Thank you for your Advices.
I'm answering about 3 of upper advice in the attachment.The part addition is difficult.
My suggestion is to use a general clock in the attachment.
It's also considered to abolish /1.001 clock rate.If there is a problem , please advise me.
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When I use tow GXB refclks(148.5MHz and 148.35MHz) and select clock in FPGA,compile error occurs.
Because GXB refclk does not connect XX_serial_refclk of SDI IP directly.
So I put SDI dmmy CH and connect refclk to Dummy CH directly.
Then compile error does not occur.
By this way,I can use GXB refclks and select them in FPGA.
Please see attachment for details.
If there is a problem, please tell me.
Honored Contributor
