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If it's possible to modify the PCB design you might consider a programmable clock generator outside the FPGA. The clock generator would feed one reference clock to the FPGA but you can reprogram it to change the frequency. Silicon Labs makes some nice parts, but there are other options.
Another trick you could try is to select the clock you want, then route that out of the FPGA and loop it back externally to the single reference clock input pin to the SDI core. This would also require a PCB change, but a much simpler one.
A third option is to just not use the 148.35MHz clock, which is only required for video standards with frame rates like 60/1.001. The /1.001 frame rates are legacy broadcast stuff and most equipment that I know of will run just fine without that divisor. You might re-check your requirements and see if you really need to support those oddball standards.
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Thank you for your Advices.
I'm answering about 3 of upper advice in the attachment.The part addition is difficult.
My suggestion is to use a general clock in the attachment.
It's also considered to abolish /1.001 clock rate.If there is a problem , please advise me.
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