Arria10 transceiver PHY rx_control[] issue

​Hi Dlim,

I think that you understand my expected placement about fPLL and Native PHY.

I attached excel file you suggested.

I seem that the pin placement in qsf is same as the pin placement in pin.rpt(actual).

Row P:User Pin assign from qsf

Row Q:Actual Pin assign from pin file

I don't configure the clocking network to x1, but "bonded x6".

I had additional questions, when I edited an excel file.

I configure pins as below.

-reference clock:I/O standard=LVDS

-transceiver PHY output:I/O standard=High Speed Differntial I/O

-transceiver PHY input:I/O standard=Current Mode Logic(CML)

I refer below URL

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf

In section 5.1.1.2, transmitter buffer should be "High Speed Differential I/O".

In section 5.1.2.1, receiver can be selected High Speed Differential I/O or CML or Differential LVPECL or LVDS.

Which I/O standard should I select ?

I can not find the DC specification about High Speed Differential I/O,CML ,Differential LVPECL ,LVDS.

BR,

taira