Arria10 transceiver PHY rx_control[] issue

HI Taira,

Ok. Now I understand your issue better.

• By right we expect Quartus fitter to assign fPLL and transceiver channel on the same bank.
• But you are seeing fitter doesn't assign fPLL and transceiver channel on the same bank.

For hard debug, sure, I can wait for you to go back office to test it out after May 31.

For now, maybe you can help me understand your expected fPLL and transceiver channel placement first ?

• Based on chip planner view, I would expect
  • fPLL#0 + NativePHY#0
  • fPLL#1 + NativePHY#3
  • fPLL#3 + NativePHY#2
  • fPLL#2 + NativePHY#1
• But you mentioned you expect below combination ?
  • fPLL#0 + NativePHY#0
  • fPLL#1 + NativePHY#1
  • fPLL#2 + NativePHY#2
  • fPLL#3 + NativePHY#3

May I suggest you to edit your Arria 10 device pin out file to show me which fPLL refclk pin and transceiver channel that you set in Quartus qsf vs what's the actual pin placement that Quartus fitter set ? This will help me understand the overall pin placement issue better.

• https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html

Also, did you configure the clocking network to x1 so that Quartus can try to fit both fPLL and transceiver channel into same bank ?

Thanks.

Regards,

dlim