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TSuzu6's avatar
TSuzu6
Icon for New Contributor rankNew Contributor
6 years ago

Arria10 transceiver PHY rx_control[] issue

Hi! In our Arria10 device, transceiver phy is configured as below, -Transceiver Configuration rules:Basic(Enhanced PCS) -PMA configuration rules:basic -Number of data channels:6 -Data rate:6144...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Taira,

Thanks for sharing the chip planner view. I have edit with comment and attached back for your reference.

  1. Sorry but it's unclear to me why are you saying fPLL#2 and NativePHY#01 doesn't belong to the same bank ? The chip planner shown that both are located on same bank, right ?
  2. Have you try to perform more debug on fPLL#2 as I suggested earlier ? Check the fPLL#2 on board clocking to ensure it's clean and stable, monitor fPLL#2 lock signal
  3. Also is there any fPLL on the same bank that you can try out by moving the PLL refclk pin to another bottom dedicated refclk pin on the same bank ?
  4. Lastly, how many failure boards that you see so far ? Does this failure happens on all your boards or just few boards ? This will helps us understand whether the issue is with hardware board/FPGA or Quartus design

Thanks.

Regards,

dlim

  • TSuzu6's avatar
    TSuzu6
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi Dlim,

    Sorry for late reply. It was a national holidy from 29-April to 6-May.

    1.Sorry but it's unclear to me why are you saying fPLL#2 and NativePHY#01 doesn't belong to the same bank ? The chip planner shown that both are located on same bank, right ?

    Ans:fPLL#02 and NativePHY#01 are located on same bank.

    In my RTL code, fPLL#i is used for Native PHY#i. So fPLL#02 is not used for Native PHY #01, but is used for Native PHY#02.

    Is this answer enough to your quesstion ?

    2.Have you try to perform more debug on fPLL#2 as I suggested earlier ? Check the fPLL#2 on board clocking to ensure it's clean and stable, monitor fPLL#2 lock signal

    Ans:No, I haven't. It is extended to close office until 31-May. So I can not go my office.

    3.Also is there any fPLL on the same bank that you can try out by moving the PLL refclk pin to another bottom dedicated refclk pin on the same bank ?

    Ans:My hardware board has two dedicated refclk pin at "bank 1D". One is used, another one is not used. The one refclk pin is distributd to four fpLLs in 4 banks.

    I will try, when I will be able to go to office.

    4.Lastly, how many failure boards that you see so far ? Does this failure happens on all your boards or just few boards ? This will helps us understand whether the issue is with hardware

    board/FPGA or Quartus design

    Ans: I see two boards. The boards are prototype and was produced only two.

    I think that fpLL#i and Native PHY#i should be located on the same bank.

    But Qurartus Prime located to different bank.

    I am worried that the definition in user SDC file or qsf file are not enough.

    Is my understand about fpLL and Native PHY location correct or not?

    Thanks.

    BR,

    taira