Arria10 transceiver PHY rx_control[] issue

​Hi dlim,

Japan is impacted too.

I confirm that "I presume you are using fPLL ? Is the fPLL sitted closer to channel [5:3] or [2:0] ? Does changing to other fPLL helps to resolve the issue here ?"

My FPGA design has 4 instances of the module is included 6CH native PHY.

This issue is occured in one instance of them.

I attach Chip Planner view with comment(.

About Chip Planner view

the issue is occured in #01.

fPLL and Native PHY in the instance #01 are not located in the same bank.

I expect fPLL and Native PHY in the same instance are located in the same bank.

Is this fitting result a resonable ?

Should I modify FPGA configuration(qsf or sdc and so on) ?

Thanks.

BR,

Taira