Hi All, I want to use the fpga to sdram path in Arria 10 HPS. I want to connect a 256bit AXI interface operating at 125 Mhz from a third party IP to this port. I had a couple of questions: I cannot select a 256 bit data width in HPS parameter editor. The maximum I can go upto is 64bits. If I want to work with 64bit data port but still match the bandwidth (32 Gbps = 256 bits * 125 Mhz) of third party IPs AXI interface, how can I really do it ? How do we decide the frequency of the clock for this fpga-to-sdram port. Which DDR protocol will QSYS configure in the DDR controller. Will it be DDR3 or DDR4. How does Qsys decide this anyway? The reason for question 4 is when I went through the Arria 10 overview document, I came to know that it supports following configurations of DDR controller in HPS. http://forum.rocketboards.org/uploads/default/original/1X/cba9db99dd96b6b24e254712be19462303c2948e.png here is the document link: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/arria-10/a10_overview.pdf I want to ensure that I can support maximum bandwidth on this path. Any suggestions/answers are welcomed !!!

do you use qsys to configure your HPS? you have to add a HPS component in this component are parameter for ram width and ram protocol as far as i know, hps ram can be up to 64 bit and you can add a fpga-to-hps-interface axi interface with up to 256 bit width don't mix up ram data witdh and axi interface width i use cyclone v fpga to hps interface with 150 MHz, Arria 10 should be more powerful

Lars_g, Thanks for the reply. Actually I am working on Arria10. When I instantiate a HPS component in Qsys, it does not have any options related to the DDR protocol or the DDR memory width like it has in Arria 5 (under SDRAM tab. The only option it gives me is to enable a conduit to EMIF. 2. You are right. In arria 5 or cyclon 5, you can have a width of upto 256 bits for Fpga-2-HPS-Sdram port, but in Arria10 the maximum width available for selection is 64 bit AXI. In Arria5 or Cyclon, you don't have to manually instantiate the DDR PHY, but what I am thinking is probably in Arria 10, I will have to manually instantiate the external memory PHY. Probably that's why, when I instantiate HPS, its parameter editor does not have any option related to DDR protocol or DDR memory width selection. Now, my real problem is, if I have only 64 bit AXI interafce to the HPS(FPGA-2-HPS-SDRAM interface), I will have to clock it at 500 Mhz to match the bandwidth of my master port(coming from a third party IP 256bit @ 125 Mhz). I am very uncomfortable with such a high frequency(even though this path is really in a hard IP). I don't understand why I cannot have a 256 bit port to HPS sdram interface like I can have in Arria 5. Why altera is limiting bandwidth on this fpga-2-sdram interface to the HPS!!! Let me know what you think.

--- Quote Start --- Lars_g, Thanks for the reply. Actually I am working on Arria10. When I instantiate a HPS component in Qsys, it does not have any options related to the DDR protocol or the DDR memory width like it has in Arria 5 (under SDRAM tab. The only option it gives me is to enable a conduit to EMIF. 2. You are right. In arria 5 or cyclon 5, you can have a width of upto 256 bits for Fpga-2-HPS-Sdram port, but in Arria10 the maximum width available for selection is 64 bit AXI. In Arria5 or Cyclon, you don't have to manually instantiate the DDR PHY, but what I am thinking is probably in Arria 10, I will have to manually instantiate the external memory PHY. Probably that's why, when I instantiate HPS, its parameter editor does not have any option related to DDR protocol or DDR memory width selection. Now, my real problem is, if I have only 64 bit AXI interafce to the HPS(FPGA-2-HPS-SDRAM interface), I will have to clock it at 500 Mhz to match the bandwidth of my master port(coming from a third party IP 256bit @ 125 Mhz). I am very uncomfortable with such a high frequency(even though this path is really in a hard IP). I don't understand why I cannot have a 256 bit port to HPS sdram interface like I can have in Arria 5. Why altera is limiting bandwidth on this fpga-2-sdram interface to the HPS!!! Let me know what you think. --- Quote End --- I think this is more complicated-- just because the upstream bandwidth is a wider bridge does not mean that the SDRAM controller is running any quicker. I believe the way it worked in the Arria V or Cyclone V was by linking together multiple ports to get increased bandwidth. You could probably do the same here and drive multiple ports, but I haven't messed with it yet. Also, the HPS on the Arria 10 does have an EMIF connection, if you want to play around with that.

Thanks Derim for the reply. You are right. The FPGA-to-HPS SDRAM interface supports six command ports each 64 bit, allowing up to six Avalon-MM interfaces or three AXI interfaces. Each command port can be used to implement either a read or write command port for AXI, or be used as part of an Avalon-MM interface. The AXI and Avalon-MM interfaces can be configured to support 32-, 64-, 128-, and 256-bit data. Since there are 4 data ports each 64bit. Look at the attached picture. What happens is, you cannot configure the FPGA2SDRAm port in HPS for a width above 64bit. This applies to following Arria10 device. 10as066n3f40I2sges. I am not sure if the tool will allow me to configure a higher data width if I use another FPGA. I am using the arria10 soc development kit and it has this device. I checked with Altera and they said that this device has some problem(probably some ECO is done) and that why this width is limited to 64 bits only. but theoretically, it can go upto 256bit. Now, 64 bit is ok, but I need a bandwidth of 32gbps on this port and to get that i will have to clock it at 500Mhz. That would be impossible for the logic which does conversion from 256bit@125Mhz to 64bit@500Mhz. Anyways, now Instead of using this port, I am using the FPGA2HPS port to access sdram through L3 interconnect. L3 interconnect works at half of cpu speed and has a 64bit interface to sdram scheduler in sdram l3 interconnect. The good thing is fpga-to-hps port can be configured as 128 bits. So my conversion logic needs to run only at 250 Mhz, which I think I will be able to manage. Let me know what you think.

Altera_Forum

Honored Contributor

10 years ago

Arria10 HPS Fpga to Sdram cannot be configured above 64 bits

Hi All,

I want to use the fpga to sdram path in Arria 10 HPS. I want to connect a 256bit AXI interface operating at 125 Mhz from a third party IP to this port. I had a couple of questions:

I cannot select a 256 bit data width in HPS parameter editor. The maximum I can go upto is 64bits.
If I want to work with 64bit data port but still match the bandwidth (32 Gbps = 256 bits * 125 Mhz) of third party IPs AXI interface, how can I really do it ?
How do we decide the frequency of the clock for this fpga-to-sdram port.
Which DDR protocol will QSYS configure in the DDR controller. Will it be DDR3 or DDR4. How does Qsys decide this anyway?

The reason for question 4 is when I went through the Arria 10 overview document, I came to know that it supports following configurations of DDR controller in HPS.

http://forum.rocketboards.org/uploads/default/original/1X/cba9db99dd96b6b24e254712be19462303c2948e.png

here is the document link: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/arria-10/a10_overview.pdf

I want to ensure that I can support maximum bandwidth on this path.

Any suggestions/answers are welcomed !!!

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Arria10 HPS Fpga to Sdram cannot be configured above 64 bits

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