Arria10 HPS Fpga to Sdram cannot be configured above 64 bits

Lars_g,

Thanks for the reply. Actually I am working on Arria10. When I instantiate a HPS component in Qsys, it does not have any options related to the DDR protocol or the DDR memory width like it has in Arria 5 (under SDRAM tab. The only option it gives me is to enable a conduit to EMIF.

2. You are right. In arria 5 or cyclon 5, you can have a width of upto 256 bits for Fpga-2-HPS-Sdram port, but in Arria10 the maximum width available for selection is 64 bit AXI.

In Arria5 or Cyclon, you don't have to manually instantiate the DDR PHY, but what I am thinking is probably in Arria 10, I will have to manually instantiate the external memory PHY. Probably that's why, when I instantiate HPS, its parameter editor does not have any option related to DDR protocol or DDR memory width selection.

Now, my real problem is, if I have only 64 bit AXI interafce to the HPS(FPGA-2-HPS-SDRAM interface), I will have to clock it at 500 Mhz to match the bandwidth of my master port(coming from a third party IP 256bit @ 125 Mhz). I am very uncomfortable with such a high frequency(even though this path is really in a hard IP).

I don't understand why I cannot have a 256 bit port to HPS sdram interface like I can have in Arria 5. Why altera is limiting bandwidth on this fpga-2-sdram interface to the HPS!!!

Let me know what you think.