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Altera_Forum
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10 years ago

Arria10 (A10) DSP block mapping problem

Dear all, I compiled the same RTL-design for both StratixV ((5SGXEA7) and Arria10 (10AX115N3), however, DSP blocks are differently used for the same VHDL description of floating-point multiplie...
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Altera_Forum
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10 years ago

The DSP blocks in Stratix V and Arria 10 are fundamentally different. Whilst Stratix V supports 36 x 36 multipliers, by using four 18 x 18 multipliers from two adjacent DSP blocks, Arria 10 does not support a 36 x 36 mode. It does discuss 27 x 27 multiplication, but only for fixed point.

Refer to the 'Variable Precision DSP Blocks' section of the Handbook for each device family and look at the 'Operational Mode' - table 1.

supported operational modes in stratix v devices (https://documentation.altera.com/#/00005262-aa$nt00072904)

supported operational modes in arria® 10 devices (https://documentation.altera.com/#/00045071-aa$aa00044854)

Do you need back to back multiplication, every clock cycle? I can only suggest you can consider performing the same calculation over multiple clock cycles. I doubt a device speed grade change will mop up that much slack - I hope you've tried that.

Cheers,

Alex