Arria V Transceivers

Hello,

I am trying to use arria V GX transceivers but I am PCB designer and I feel a little lost in this field. I want to transmit a 960 Mbps data rate to a main board from a daughter board. I can use only one channel to do this (one tx channel in the daughter board and one rx channel in the main board) and I would like to know what resources I will need.

The daughter board has a DDR2 memory with a image which I have to send to the Main board by means of a data flow, this flow has to have the recovery clock included, I think this is possible using 8b/10b codification. My question is basically if, besides the tx channel and the rx channel, I need a input transceiver clk (generated by a external oscillator of 120MHz (8bits*120MHz=960Mbps)) in each FPGA, in the daughter board to generate the data flow and in the main board to recovery it.

Thanks in advance.