Arria V Transceiver Native PHY width issues

Hi.

According to the document Transceiver Architecture in Arria V Devices page 10, the Native PHY should be able to support rates up to around 10G in PMA direct mode, while offering a number of different input widths. These are 8, 10, 16, 20, 64 and 80 bits. This is also documented in the transceiver user guide.

I have a project where I have created such a Transceiver with a data rate of 6G and interface width of 20 bits. The core creation in MegaWizard is error free and looks like this:

https://www.alteraforum.com/forum/attachment.php?attachmentid=7275

However, during compile I get an error like this:

Error: Clock Divider Parameter 'data_rate' is set to an illegal value of '6000.0 Mbps' and PMA Direct parameter is set to 'true'. If PMA Direct is false, the value is illegal for protocol mode: '' with a device speed grade of '5_H3', PMA WIDTH of '' and byte serializer mode : '' and latency '' on atom 'jesd204b_eval_core:eval_core|transceiver:transceiver_inst|altera_xcvr_native_av:transceiver_inst|av_xcvr_native:gen_native_inst.av_xcvr_native_insts.gen_bonded_group_native.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts.av_tx_pma_ch_inst|tx_pma_ch.tx_cgb'. If PMA Direct is true, the value is illegal for PMA-PLD WIDTH of '20'.    Info: "1000.0 Mbps to 3200.0 Mbps" is a legal range
Error: Channel PLL Parameter 'output_clock_frequency' is set to an illegal value of '3000.0 MHz' and PMA Direct parameter is set to 'true'. If PMA Direct is false, the value is illegal for protocol mode: '' with a device speed grade of '5_H3', PMA WIDTH of '' and byte deserializer mode : '' and latency '' on atom 'jesd204b_eval_core:eval_core|transceiver:transceiver_inst|altera_xcvr_native_av:transceiver_inst|av_xcvr_native:gen_native_inst.av_xcvr_native_insts.gen_bonded_group_native.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas.rx_pma.rx_cdr'. IF PMA Direct is true, the value is illegal for PMA-PLD WIDTH of '20'.
    Info: "500.0 MHz to 1600.0 MHz" is a legal range

If I change the width to 64 or 80 bits in MegaWizard, everything works just fine.

So it seems like it is not possible to use the 20 bits interface for rates higher than 3G when using Arria V Transceiver Native PHY?

Edit: I ahve tried with Quartus 12.1.sp1 and 13.0 - same results.

Regards,

Hytzon