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Altera_Forum
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12 years ago

Arria V LVDS IO

Hello, Knowledge base (http://www.altera.com/support/kdb/solutions/fb128391.html) states: "You must assign the LVDS I/O standard-enabled pins in the right I/O bank as PLL clock input pins only"...
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Altera_Forum
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12 years ago

Thanks fpgabuilder!

What is confusing to me is that those none of the pins on the right side of the device support LVDS - not even the clock input pins. At least this is true for 13.0dp1. I am not using any PLL inputs on that side, but I am using some of those pins as regular I/O.

Are you saying that those pins shown as "PLL/DLL related" should only be used for PLL inputs?

If that is the case, one of those pins is a DQS (pin T1 in your device), which pretty much makes that DQ group unusable for DDR -- does that sound correct?

Thank you!