Arria V FPGA overcurrent

Vref is located on a double function pin.

It can be used as the reference voltage input if you use a voltage referenced I/O standard or as a user I/O (see A5 pin connection guide line).

Therefore, the absolute max rating of VI DC input voltage apply (see A5 device handbook, Electrical Characteristics, VI DC input voltage Min: –0.50/ Max: 3.80 V).

Nevertheless, in my previous HW design, I found Altera FPGAs rather robust wrt unfortunate manipulations (I/O short-circuit or overvoltage for instance) but ...this is just a feeling.

It seems you have removed the FPGA on your 1st board, so you can check on the PCB pads of every FPGA power supply pins that the correct supply voltage is applied (it's a long way I know...) or at least perform an exhaustive check on the PCB gerber files.

You said also "we lost for sure the FPGA but maybe also this board in the removing process."

=> A "latch-up" state is not necessarily destructive provided it does not last too long.

More over,removing BGA packages and putting solder balls back is a current process you can subcontract at a reasonable cost (TB compared to the FPGA price of course ...)

Anyway, once you are 100% sure of your FPGA power supply pins routing on the PCB and of your Vref, you can turn on the 2nd board with the current limitation of its external power supply activated and wo/ configuring the FPGA in order to have only the static power consumption. By monitoring the Icc and gradually increasing the power supply current limit up to the expected level, you will avoid any electrical destruction.