Altera_Forum
Honored Contributor
Honored ContributorARRIA V clk PINS
Hello
In the most updated Pin Connection Guide (PCG-01013 from January) the clock pins are defined as input pins: CLK[0:23][p:n] Clock, Input Dedicated positive & negative clock input pins that can also be used for data inputs. OCT Rd is supported on these pins. Connect unused pins to GND. In addition, all unused CLK pins should be connected to GND. On the contrarry,on the PINOUT and QUARTUS II sotware those pins are described as IO's. 7A VREFB7AN0 IO CLK13p DIFFIO_RX_T3p DIFFOUT_T3p A6 DQ1T DQ1T DQ1T 7A VREFB7AN0 IO CLK13n DIFFIO_RX_T3n DIFFOUT_T3n B6 DQ1T DQ1T DQ1T I would like to know for sure -are these pins input-only pins or can they be also outputs/bidir pins?
