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Honored Contributor
Honored ContributorArria V - LVDS Serdes
Hi,
I am using Altera megafunction "ALTLVDS_RX" for deserializing CameraLink data. settings are: Number of output channels: 4 Deserialization factor: 7 Input data rate: 280 Input clock: 40MHz Quartus version 15.0 The data input signals (LVDS) are X0, X1, X2 and X3. the analysis & synthesis reports following:warning (15610): no output dependent on input pin "x1" When I check RTL Viewer or post fitting viewer, the IO_IBUF of signal X1 has no outputs but for X0, X2 and X3. Therefore signal X1 is not connected to the deserializer input. Another proof is that the timing analyzer doesn't report any RSKM timing for X1 but for all others. In the design file, all my data inputs X0 to X3 are directly connected to the deserializer input. Why does Quartus gets rid of my data signal X1? Any issues in the IP? Your help is appreciated.
5 Replies
Altera_ForumIs the output channel of the megafunction associated with the X1 input tied to any processing/logic "down stream" from the deserializer? If not, the compiler might be "synthesizing away" the receiver channel that it believes is "unused".
- Altera_Forum
If you try running Modelsim simulation, is the X1 channel manage to output any data?
- Altera_Forum
Which Quartus II version are you using? Probably you could try with different version to see similar observation?
- Altera_Forum
Thank you very much for your help; problem solved.
From the deserialized output data (27bits) I only use 8bit. The 8bits are mapped form the LVDS input ports X0, X2 and X3 but not from X1. I changed design now to 10bit with bit no. 9 mapped from LVDS input port X1. Now the software keeps the all inputs. :-) - Altera_Forum
Glad to hear that you have managed to solve it.
