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Altera_Forum
Honored Contributor
13 years agoPrevious FPGA families (upto Cyclone II/Stratix II) had quite noise sensitive 1.2V analog PLL supplies. Since Cyclone III/Stratix III, an on-chip regulator reduces the PLL noise sensitivity considerably. Some Altera development kits for the older FPGAs came with separate linear regulators for the PLL supply. I believe that it had been possible to get sufficient power supply quality for these devices with switched supplies and passive filters, but linear regulators have been at least reasonable in this special case.
For newer FPGAs, linear reguator might be still meaningful for low load supply nodes, e.g. 2.5V with only a few LVDS IOs, or even VCCINT of small FPGAs with low core clock frequency and moderate switching activity. But we also have small switching regulators with low external part count.