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If its that consistent, then its likely a data format error. The error may have nothing to do with those bytes though, it likely takes multiple clocks internally to check previously loaded data bytes.
If the error was not consistent, I would tell you to check the DCLK edge signal integrity. If your observations are repeatable, then check whether you are serializing data correctly.
That was a poor design decision. You should always include the JTAG port.
Cheers,
Dave
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yes, the design was bad. unfortunately I will have to deal with it.
the error is consistent. always between the 62k th packet and 62,999th.
the INIT_DONE pin stays high all the time. is that normal ? I though it should go low after 3 DCLK periods.
(I have pulled the INIT_DONE to 2.5V with a 10k resistor)
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