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If its that consistent, then its likely a data format error. The error may have nothing to do with those bytes though, it likely takes multiple clocks internally to check previously loaded data bytes.
If the error was not consistent, I would tell you to check the DCLK edge signal integrity. If your observations are repeatable, then check whether you are serializing data correctly.
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I am sending the LSB on data0 and MSB on data7. DCLK has a period of 18ms, with 50% duty cycle, so I believe all of this is correct.
the thing that bothers me most is that CONF_DONE never goes high. It is pulled high to 2.5V through a 10kohm resistor, but never released by the FPGA. what does this mean ?
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