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I have checked more in detail, and nSTATUS actually always goes low between the 62.000th and 62.999th byte.
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If its that consistent, then its likely a data format error. The error may have nothing to do with those bytes though, it likely takes multiple clocks internally to check previously loaded data bytes.
If the error was not consistent, I would tell you to check the DCLK edge signal integrity. If your observations are repeatable, then check whether you are serializing data correctly.
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I do not have access to a JTAG port for the FPGA, so this is unfortunately the only way I can troubleshoot it.
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That was a poor design decision. You should always include the JTAG port.
Cheers,
Dave
Honored Contributor
