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nome's avatar
nome
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Arria II GX configuration from CPLD

Hello, I am using the JS28F256M29EWH NOR Flash with only using 8-bit data and 25-bit address Parallel Flash in FPP mode. In my case, our flash 8-bits flash data pins are directly connected with fpga...
Configuration
NurAiman_M_Intel's avatar
NurAiman_M_Intel
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,


Thank you for contacting Intel community.


What do you mean by "configure Arria II GX with CPLD EPM240T100I5 without PFL using Config_Control_Codes from Intel Altera Stratix II"? What is the reason on using Config_Control_Codes from Intel Altera Stratix II for Arria ii?


What Quartus version do you used?


Any error shows?


Regards,

Aiman



nome's avatar
nome
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hello,

Thank you for your reply.

What do you mean by "configure Arria II GX with CPLD EPM240T100I5 without PFL using Config_Control_Codes from Intel Altera Stratix II?

I am not utilizing PFL (parallel flash loader) due to the limited LE (logic element) blocks available, as the EPM240T100I5 CPLD has only 240 blocks. This restriction prevents the use of a higher-density CPLD.

We need to allocate more space for various functionalities, aside from FPGA configuration. This is why we are using the official config_control_codes from Stratix, as indicated in the attached QAR file in my initial post.

All specific pin requirements, such as fpga_addr, fpga_nSTATUS, fpga_dclk, and others, have been assigned according to our custom board specifications. However, the issue is that these codes are not working; when testing fpga_dclk from the oscilloscope, it remains low at all times.

Thanks,

Nome