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Honored Contributor
Honored ContributorArria II DDR2 clock assignment
Hello, I am trying to use 2 x16 DDR2 chips and combine them as 1 x32 DDR2 using the HP DDR2 IP. I am using differential DQS and have one CK/CK# pair per chip. In the emi_plan_pin document...
Altera_ForumHonored Contributor
Honored ContributorJake, thank you for the feedback!
What I ended up doing was put both CK/CK# pairs in one x4 DQ group. Quartus does no complain about it (but then again, it did not complain when I had them in different DQ groups.) What is confusing in the Altera documentation is when they say "the same DQ group", it is not clear if they meant the same DQ group as the DDR2's DQ/DQS signals associated with that CK/CK# pair or that the CK/CK# pairs share "a" DQ group. Once the layout is done, I should be able to plug in the trace model and I will have a better TimeQuest analysis. I will post the results then. Thank you for your help.
