New Contributor
New ContributorI've attached the entire configuration block for the FPGA. U19 in the upper right corner is used to disconnect the processor SPI bus from the PROM/FPGA. The signal FLASH_FPGA_EN is pulled low. All the other control/status signals are connected directly to the processor. I have the processor disabled which tri-states those pins. That means that the pull-up/pull-down resistors are controlling the FPGA load operation at power-up. We have also successfully programmed the PROM and verified the contents using this interface.
I needed to get wires attached to the board to do the scope captures. I will get them to you as soon as possible, The nSTATUS line I believe is toggling. I will get more specifics when I can get the scope pictures.
As for the cross-reference table, it was from Micron and I misinterpreted it. I was looking at the A10 SoC line and not the general A10 line. There is one thing I noticed. Micron implies that the MT25QU parts will only work in Passive Serial mode. I'm assuming that Intel has verified that they work in Active Serial mode as well.
Regards,
Jim Cassey
