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Altera_Forum
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9 years ago

Arria 10 SX - The Fitter cannot place logic IO_LANE ???

Hello, Actually, I use a Reflex CES Achilles board with a SoC FPGA Arria 10 (10AS066H4F34E3SG). The board is also equipped with two DDR4 memory (2x8 GB). One of them can be accessible from the ...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Without looking at your attachment, I'd go back into Qsys and the IP Parameter Editor for the HPS. If there are I/O conflicts, they should be flagged there. You shouldn't have to make changes in the Pin Planner since your choices in the IP Parameter Editor determine which pins to use for the memory interface. Also, if you happen to be using Quartus Prime Pro, try using BluePrint. That might help to isolate what is conflicting.