Honored Contributor
Honored ContributorI found a solution. This is what we did, may it will help someone else.
The Preloader software (SPI) expect the QSPI (HPS Flash) to be in a 3 Byte mode (the default at reset). In our application we set-up the QSPI device to 4 Byte mode in U-Boot. At power on, the QSPI device is in 3 Byte mode, and the preloaders are happy. If we type reset into u-boot, our CPU resetted (e.g. HPS_nRST bi-dir signal), but our QSPI device reset in was not connected to this signal. Therefore when the preloaders started our QSPI device is in the wrong mode. The solution is to tie HPS_nRST, HPS_POR, Byte Blaster pin 6, our External watchdog power on reset device reset out, QSPI reset in and the DDR 1V35 PGood output (All open collector) together. Tested and working. However, i could not find any documentation stating whether the Byte Blaster pin 6 is open collector or not. Luckily we had a series resistor in between which we changed to a 1K. Next PCB, we will add a open collector buffer between pin 6 of byte blaster and this single Open Collector reset. Note If pin 6 of the Byte Blaster is not connected to the HPS_nRST, we found that DS5 did not start up every time. Hope it helps.
