[Arria 10 SoC] QSPI Flash GigaDevice Compatibility (GD55LB02GE / GD55LB02GF)

Good question, and I understand the urgency given the pricing situation. Let me work through your three questions carefully based on what's documented for Arria 10 SoC.

1. Arria 10 SoC HPS BootROM Compatibility with GigaDevice

GigaDevice is not listed in the Supported Flash Devices for Arria 10 SoC page — you've confirmed that yourself. The specific parts GD55LB02GE and GD55LB02GF do not appear anywhere in my available documentation for Arria 10 SoC HPS boot support, so I cannot confirm or deny them as verified boot devices.

What I can tell you is what the Boot ROM actually requires, so you can assess compliance yourself:

• The boot ROM code configures the QSPI controller to default settings for the supported SPI or quad SPI flash memory. Arria 10 SoC Boot User Guide Those defaults are fixed — the Boot ROM does not parse JEDEC SFDP at boot. It uses hardcoded register values.
• The read opcode in non-XIP mode is rdopcode in the devrd register = 0x3 (for normal read) and 0xB (for fast read). Arria® 10 Hard Processor System Technical Reference Manual Your GigaDevice part must support both of these standard opcodes.
• The default instruction type is Single I/O (1 bit wide); the address transfer width (addrwidth) and data transfer width (datawidth) of the devrd register default to 0. Arria® 10 Hard Processor System Technical Reference Manual
• The number of address bytes defaults to 3 bytes (numaddrbytes in devsz = 2). Before a reset, you must ensure that the QSPI flash device is configured to 3-byte address mode for the boot ROM to function properly. Arria® 10 Hard Processor System Technical Reference Manual
• BSEL value 0x6 selects a 1.8 V quad SPI flash memory. Arria® 10 Hard Processor System Technical Reference Manual

For a 2 Gb (256 MB) device, 3-byte addressing only covers up to 128 MB (16 MB address space). The Boot ROM only needs to reach the second-stage boot loader (SPL/preloader), which is located at offsets that are multiples of 256 KB Arria 10 SoC Boot User Guide — so 3-byte addressing is sufficient for the boot stage as long as the SPL image fits within the first 16 MB. The concern is that after the SPL runs, it may switch the flash to 4-byte mode; if a QSPI flash has been switched to 4-byte addressing during operation, you need to ensure it is returned to its default 3-byte addressing mode whenever the HPS is reset, otherwise the HPS cannot boot from or access the QSPI chip. Methods include asserting the flash reset pin on HPS reset, or power-cycling the flash. QSPI Flash Interface Design Guidelines

Also critical for your board design with BSEL=0x6: The QSPI_SS1 pin is also used as BSEL0. When selecting BSEL=0x6 (1.8V QSPI), QSPI_SS1 cannot be directly connected to the QSPI chip select. As HPS BSEL values are sampled on cold reset deassertion, you must decouple QSPI_SS1 from the chip select — for example, via an external buffer with a pull-up on the flash side. Once the HPS exits cold reset, QSPI_SS1 is driven correctly. QSPI Flash Interface Design Guidelines

2. GD55LB02GE vs. GD55LB02GF

Neither part number appears in any available Altera documentation for Arria 10 SoC. I cannot make any statement about JEDEC ID parsing, SFDP compatibility, or Boot ROM support for either revision. The distinction between the E and F revisions is entirely outside the available documentation.

The design guidelines recommend using an "Intel Tested and Supported" device if at all possible, to minimize development effort and eliminate incompatibility risk. The next-best option is a "Known to Work" device — one compatible with Boot ROM and proven with at least one bootloader — but that may not have HWLIBs, OS support, or HPS Flash Programmer support. Flash Device Driver Design Considerations

Practically: if you want to qualify a GigaDevice part, you'll need to verify against the Boot ROM opcode requirements above, and you'll need to validate the U-Boot/SPL driver separately since GigaDevice is not on the officially supported list for Arria 10 SoC.

3. HPS Flash Programmer (quartus_hps) Support

The HPS flash programmer supports Quad SPI (QSPI) Flash and ONFI-compliant NAND Flash. Quartus® Prime Pro Edition User Guide The HPS Flash Programmer supports Arria 10 SoC devices. Altera SoC FPGA Embedded Development Suite (SoC EDS) User Guide However, the programmer identifies flash by silicon ID: the quartus_hps programmer may fail during programming if the QSPI contains an existing or corrupted image. Error messages include "Fail to read Silicon ID" and "Quad SPI Flash silicon ID is 0x00000000." Why does quartus_hps fail to reprogram my QSPI device?

The only GigaDevice part confirmed in the available Quartus Prime programmer supported-device table is the GD25Q127C (3.3 V, 128 Mb) — your 1.8 V 2 Gb GD55LB02GE/GF parts are not listed. This means quartus_hps may not recognize their silicon IDs and could fail.

Your fallback options if direct quartus_hps programming fails:

• The Customizable Flash Programmer enables users to program third-party flash devices (Winbond, Macronix, Cypress) with an FPGA configuration bitstream or raw programming data (.rpd) via System Console. This design example is the Programmer Image for Arria 10 FPGAs. Design Details You can adapt the TCL scripts for GigaDevice opcodes — the TCL script can be customized to perform any quad SPI flash command, such as programming flash registers to set 4-byte addressing, dummy clock cycles, and the quad enable bit. Customizable Flash Programmer User Guide
• For HPS boot image programming specifically, U-Boot's flash commands are a fully supported alternative path, as described in the Arria 10 SoC design guidelines.

Summary / Recommendation

GigaDevice is not an officially supported or validated vendor for Arria 10 SoC HPS boot in the available Altera documentation. If you proceed, you'll need to: (1) verify that your chosen part supports standard 0x03/0x0B/0xEB read opcodes in SPI mode at power-on; (2) ensure the flash starts up in 3-byte address mode (or implement a hardware reset scheme as described above); (3) plan for U-Boot/SPL driver development or adaptation; and (4) expect that quartus_hps may not natively recognize the silicon ID and use the Customizable Flash Programmer or U-Boot as your programming path instead.

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Thank you very much.