New Contributor
Regular ContributorHi,
Was there any error reported from Qsys/Platform Designer when generating the HDL?
New ContributorHi @EberL_Intel
There's no error in the Qys when generating the HDL.
I had a working Avalon Master (FPGA Side) connected to F2H Bridge design.
Due to my requirements, I changed the Avalon interface (FPGA Sise) in that working design with AXI MM interface by using a proven Avalon to AXI MM Wrapper.
In the Qys, I have done the required changes for AXI MM interface and connected them with F2H Bridge.
Currently, I am not regenerating the software binaries. ie, SD Boot files. Is there a necessity to regenerate the fsbl, uboot, dtb etc for my above change?
Regards,
Shenoy
Regular ContributorHi Shenoy,
I apologize for the delay in response.
Yes, for your case, you have made changes with the connections to the HPS in Qsys, you will have to regenerate the uboot, dtb etc, as these handoff files are based on the HPS settings that was made from Quartus.
Hopes this information helps.
Also, we do not have an Arria10 example design available with FPGA AXI4 Master connecting with HPS Slave F2H bridge.
We do however have a Arria 10 SoC guidelines for interconnection the HPS and FPGA of the Arria 10 SoC to help you:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an-a10-soc-device-design-guidelines.pdf
Regards,
Eber.
