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Shenoy's avatar
Shenoy
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6 years ago

Arria 10 SOC - FPGA to HPS Bridge : Connecting FPGA AXI4 Master to HPS Slave

Hi, I want to connect AXI4 Master in the FPGA to the HPS. In the Qsys, I've connected my AXI4 master with f2h slave in the Arria10 HPS. What I see during testing this implementation is that the sla...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
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6 years ago

Hi,

Was there any error reported from Qsys/Platform Designer when generating the HDL?

Shenoy's avatar
Shenoy
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6 years ago

Hi @EberL_Intel​

There's no error in the Qys when generating the HDL.

I had a working Avalon Master (FPGA Side) connected to F2H Bridge design.

Due to my requirements, I changed the Avalon interface (FPGA Sise) in that working design with AXI MM interface by using a proven Avalon to AXI MM Wrapper.

In the Qys, I have done the required changes for AXI MM interface and connected them with F2H Bridge.

Currently, I am not regenerating the software binaries. ie, SD Boot files. Is there a necessity to regenerate the fsbl, uboot, dtb etc for my above change?

Regards,

Shenoy