Honored Contributor
Honored ContributorHi Mike,
Let me first state that its difficult to synchronize an external clock with a PLL generated clock. This is due to the PLLs inherent design. PLLs are Analog/Digital blocks which have feedback loops inside. Thus when a PLL locks onto a clock and begins to generate its own derived clocks.. there will be some amount of delay introduced which will cause a shift in the output clock with reference to the input clock. It may be possible to correct this at times (depending on the PLL implementation in the FPGA) using jitter or phase shift mechanisms. For most designs where the generated clocks have to be synchronized with the source clock, the solution is to generate another clock with the same frequency and time parameters as that of the input clock along with the generated clocks. You can then have the PLL synchronize the generated clocks to their respective edges. This way you will have two clocks that are synchronous to each other in phase with one being exactly same frequency as that of the input clock. For example, Input clock to PLL = 25MHz Desired output clock1 = 100MHz Desired output clock2 = 150MHz , both these clocks need to be synchronous with the input 25MHz clock. The way to achieve this is have the PLL generate all 3 clocks : Input clock = 25MHz O/p clock1 = 25MHz O/p clock2 = 100MHz O/p clock3 = 150MHz Then set the PLL to synchronize all three output generated clocks in phase and use Jitter correction if needed. This way you will have the synchronous clocks you need for the design. Hope this helps!
