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BHoey's avatar
BHoey
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6 years ago

Arria 10 HPS peripheral routing - EMAC/MDIO - Shared IO/FPGA IO

I need to repurpose some IO in a HPS Shared IO sub-bank that contains the MDIO pins. These repurposed pins need to be driven from the FPGA fabric. A Shared IO sub-bank cannot only be HPS-driven OR ...
BHoey's avatar
BHoey
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6 years ago

You cannot do RGMII via the FPGA.

I looked into routing MDIO to FPGA and RGMII to the Shared IO. Could not find a solution.

I tried routing EMAC0 to shared IO with the MDIO off. I then tried routing EMAC1 (which I do not need) to the FPGA just for the MDIO. This became too involved in software to get EMAC0 to use the MDIO of EMAC1. I would think there would be some example of how to do this as dual or quad PHYs would use 1 MDIO for multiple MAC.

Ultimately I found we had the trace pins reserved with resistors to open pads on the PCB. As we were not using the trace we re-purposed by tacking wire to the resistor pads.

Thanks

-Brian