Arria 10 HPS peripheral routing - EMAC/MDIO - Shared IO/FPGA IO

Hello Brian, Can you look at the HPS technical reference manual in below link Figure 120 and Figure 121 ? https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_5v4.pdf Either using custom logic or using the IP you can use route to the FPGA PAD. Bit confused with your question, you want MDIO is routed to FPGA and MAC signal routed via HPS Shared IO ? Thank you , Regards, Sree