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gschuell's avatar
gschuell
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2 years ago

Arria 10 HPS EMIF DDR3 Calibration Failure

I am bringing up a custom Arria 10 SX board and have been running into issues with getting my DDR3 SODIMM to calibrate when connected to the HPS EMIF conduit. The EMIF example design calibrates pro...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Greg,


"Given that the EMIF example design passes calibration (at least per the local_cal_status_pass signal), can you think of anything that would cause the HPS to fail other than something in the HPS design structure, timing errors, or the U-Boot SPL bootloader configuration?"

  • From the EMIF perspective, we always check the HPS EMIF design by implementing FPGA EMIF interface with HPS EMIF pinout. So then we can check the issue in between the memory and FPGA device.
  • But then there is no issue at EMIF part.


"Does the HPS calibration do anything different that what occurs during the EMIF example design calibration (e.g. the EMIF always exercises the same address, but the HPS does a more exhaustive memory test)?"

  • No, it's run through similar process as describe in the User Guide.


"Or should any DDR3 memory configuration that passes calibration for the EMIF example design always pass when combined with the HPS EMIF conduit?"

  • It's should be passed calibration as well as FPGA EMIF design.


"For the HPS test, I am programming the full FPGA bitstream (i.e. not using Early Release mode) via JTAG and then running the ARM DS bootloader script from RocketBoards to load and execute the SPL initialization code. Does this seem like the best way to test the HPS calibration, or should I try another method?"


Regards,

Adzim


gschuell's avatar
gschuell
Icon for New Contributor rankNew Contributor
2 years ago

Hi Adzim,

We did some more testing with the EMIF example design with various configurations on both our custom board and the Arria 10 SoC Development Kit. I've attached a spreadsheet detailing the results as well as a document describing the board skew information (trace lengths are shown in mm and skew is calculated in ps).

Based on these results, it appears that we pass the "local_cal" in all configurations on both boards with what to our eyes appear to be equivalent (or in some cases better) timing margins.

But for the dev kit, in all configurations (regardless of PLL, memory clock, or Half/Quarter rate user clock), we always additionally pass the traffic generator test.

On our custom board, it looks like we pass the traffic generator test when we are operating in quarter rate user clock mode, but in half rate user clock mode we don't get any result from the traffic generator test (no pass, fail, or timeout). Do you have any idea what could cause this? I would at least expect a fail or timeout if there was an issue detected during the calibration.

Also, when I step through the U-Boot SPL code in the debugger on the HPS design, I am seeing the code jump to an error handler that says to "hang forever" very close to a comment that says that the MPFE hang workaround should be complete. This looks like it would be just before or possibly during DDR calibration. The MPFE seems to refer to the "Multi-port Front End" memory arbiter. Any ideas what could cause this?

Thanks,

Greg