Forum Discussion
Hi Greg,
Thank you for the information.
I have checked the EMIF setting with the given memory datasheet.
Some of your setting may not be accurate as stated in the datasheet.
I may suggest you to compare with the snapshot that I will attach later.
For HPS EMIF design in custom board, do you see any timing issue in the timing report?
I like to suggest you to perform the board simulation first to get the accurate skew information because this part can be a potential cause of the calibration issue.
Regards,
Adzim
- gschuell2 years ago
New Contributor
Hi Adzim,
Thank you for sending the updated parameters. I have applied the suggested settings and retested with similar results (i.e. EMIF example design passes local calibration with similar margins and HPS fails to calibrate and/or hangs on U-Boot SPL).
I did have some additional questions:
1. We are currently testing with a memory clock of 400MHz (DDR3-800) with the thought that slowing down the memory interface would give us the best chance of successful calibration. Is this a good idea, or should we run at the rated DDR3-1600 speed of the SODIMM?
2. Are the settings you provided taking into account our memory clock of 400MHz, or should we make additional adjustments (such as dropping our CAS latency to 6 and write CAS latency to 5)?
3. For tRRD, tWTR, and tRTP, you changed the values from 4 cycles to 3. Is this correct per pg. 81 of the memory datasheet? Also, would you set tFAW to 50ns for DDR3-800 or 40ns for DDR3-1600 since we're using x16 devices?
4. Since the EMIF example design passes calibration, are there things specific to the GHRD that we should be looking at (e.g. reset, PLL lock status, any debug registers, etc) to let us know the status of the calibration?
Thanks,
Greg
- gschuell2 years ago
New Contributor
Hi Adzim,
I also got some skew information from the board designer and have attached it here. Did not notice a major difference in the results when applied.
Thanks,
Greg