Arria 10 HPS EMIF DDR3 Calibration Failure

Hi!

"The EMIF example design calibrates properly using the same timing parameters as I have in the HPS project."

• Can you share the pin connection of the EMIF interface in the EMIF example design?

"Most of the debug guidelines suggest getting the example design to calibrate successfully and then use those settings for the HPS project, but what other things could cause the calibration failure only on the HPS side?"

• After confirming with FPGA EMIF that the memory and device is working properly, then need to check on U-Boot side.

"Are there any debug interfaces that could be useful in gathering additional calibration status information?"

• Unfortunately we don't have a debug interface to debug the HPS EMIF IP directly.
• To debug the HPS EMIF IP, we instantiated a FPGA EMIF interface at the HPS IO Bank and checked the calibration report from EMIF Debug Toolkit.

Regards,

Adzim