Arria 10 GX FPGA with PCIe core no coreclkout_hip

Hi KhaiY,

We had the board with the Arria 10 reworked and now have a 100 MHz oscillator connected to the CLKUSR pin.

When we power on the board connected to the PCIe backplane, we see the link come up.

This did not happen before the rework, so the CLKUSR appears to be getting the 100 MHz clock.

We also have a Teradyne Lecroy Summit T24 PCI Express 2.5/5.0 GT/s box to help analyze the PCIe traffic.

On the analyzer, we see it starts at 4 lanes of Gen1 (2.5 Gbps) rate.

Then it tries to switch to Gen2 rate (5 Gbps) and fails.

It reverts to 2 lanes (channels 3 & 2) at Gen1 rate.

We were wondering if we need to do configuration or calibration in the Arria 10 for the transceiver links?

Or is there something else we could look at or try to see why the data is not being accepted?

Thanks.