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2 Replies
- Altera_Forum
Honored Contributor
This gets configured in the EMIF controller parameter editor when you add the controller through the IP catalog or in Qsys. It's handled automatically by the controller during memory initialization. See this online training:
https://www.altera.com/support/training/course/omem1122.html - Altera_Forum
Honored Contributor
Hi
Thanks sstrell. The section 3.4.1 of "JEDEC DDR4 SDRAM Specification" says that "Mode Registers can be altered by re-executing the MRS command during normal operation." In case if I want to do the same in my simulation (i.e rewrite to MR register after initialization), how can I achieve it in Arria 10 EMIF Simulation Setup Thanks & Regards S.T.Saraswathy