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Altera_Forum
Honored Contributor
8 years agoHi Tzi Khang
Thank you for your advice. My design occupies only 30% of Arria 10 device. Is it related to this matter on AN370? Back to my question, A.jic file does not always cause failure. Once B.jic file has been written, after that, I can use A.jic file also without any failure. So A.jic file might be some trigger for FPGA malfunction, however another cause would be there. Especially TDO port failure, TDI throughout, is strange symptom. Can bad program file affect to dedicated JTAG port? Although I have been checking Altera-Intel documents, I have not find such throughout mode on TDO-JTAG so far. Regards, Tetsuya