Array of interfaces in SV

Does anyone know how to deal with the array of interface scenario presented in this thread if you were to add some input ports to the interface?

Example:

interface iface(input logic clk)

logic a;

logic b;

modport mport (input a, output b);

endinterface

** How would you instantiate the array of interfaces so each interface in the array could have it's own clk wired to a unique clock? If I do as follows:

iface top_iface_array [3:0] (.clk (my_clk));

I have only wired up to a single clock and it really doesn't make sense when I'm referencing an array of interfaces.

Thanks.

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You can do it, but you have to do it a certain way for Quartus to synthesize it. The module port must be an unpacked array of interface modport's. You need an unpacked array of interfaces to connect to it. When you instantiate the module, make the port connection with the name of the interface array only, not the modports.

interface iface();
    logic a;
    logic b;
    modport mport(input a, output b);
endinterface
module mod (
    iface.mport iface_array 
);
    ...
endmodule
module top ();
    iface top_iface_array  ();
    mod mod_inst(.iface_array(top_iface_array));
    ...
endmodule

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