Array in Verilog

--- Quote Start ---

Hi, I want to create an array like this

reg [7:0] mem [0:3];

I want to initialize mem such that mem[0] = 2, mem[1] =4 , mem[2] = 1, mem[3] = 5. how to do that?

--- Quote End ---

Hi,

add an initial sequence to your code like this:

reg [7:0] mem [0:3];

initial

begin

mem[0] = 2;

mem[1] = 4;

mem[2] = 1;

mem[3] = 5;

end

Kind regards

GPK