Aria V Display Port core sometimes disconnected

Hi dlim

We are using the IP catalog core from Quartos 15.0, I guess it is Intel Altera core but many of the generated files contain the word "bitech" on it. (see attachment). We intend to meet the local FAE tomorrow and check this issue.

Regarding the lock signal I mentioned earlier - I'm sorry for the confusion - I was referring the MSA - lock that can be generated on the QSYS GUI as a trigger(see attached image)

My signalTap also contain the below Transceiver Native PHY signals:

• Rx_is_lockedtoref
• Rx_is_lockedtordata

I assume the first is indicating on ref clock signal integrity and the second on display port data signal integrity?

Regarding the signal integrity issue,

• Scope and probe BW are 4GHz
• Probe was soldered to tips on board and was clumped to the PCB.
• 100ohm OCT was not helpful

Regarding your question on how we verify the video – we output the digital video signal from the Aria V in to external video encoder which convert it to analog screen. I was looking for the transceiver toolkit feature you mentioned but didn’t find such option. Can you please send me more info on how to use this feature?

However after I reviewed the brd file I found out the LVDS clock pins, though short, have no ground plan above or below the clock signals. I suspect it is the root cause for the noise. In order to lower the clock noise I replaced the 162MHz clk with 50MHz clk and use Alt PLL to convert the clock back to 135MHz. It looks like the signal is less noisy now (see attached image).

I’m running some tests to see if the failure is resolved or can be recreated again. Will update as soon as I have some answers.