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relsaar's avatar
relsaar
Icon for New Contributor rankNew Contributor
5 years ago

Aria V Display Port core sometimes disconnected

Hi All We have a PCB board we designed with AMD 8860 GPU that sends DP video to Aria V Display Port core (Qsys). In some of our boards we sometimes have DP connection issues. The video signal goe...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Ariel,


I looked at the KDB link. You can see at the top, it mentioned the affected FPGA family is just Arria 10 and Stratix 10 which means Arria V is not affected by this issue.

  • Anyway, I always recommend user to upgrade to latest Quartus Standard edition version if possible to mitigate the risk of known issue from older Quartus version.


Btw, you mentioned Rx loose lock. Are you referring to Rx channel CDR locked to data signal or some other status signal ?

  • Common factor that will caused CDR to loose lock are like below
    • high PPM different on CDR refclk - checked your on board crystal or clock generator quality.
    • Bad signal integrity on CDR refclk - same debug approach as above
    • Bad signal integrity on data transfer on Rx channel - reduce your video resolution to reduce the DP bandwidth from 5,4G to 2.7G or even 1.67G to help isolate signal integrity issue
  • You can also use DP example design to dump the MSA log to check if you observe high bit error rate (BER) on the 4 DP channel or 2 DP channel


Thanks.


Regards,

dlim


  • relsaar's avatar
    relsaar
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi dlim

    Thank you for your fast and detailed response.

    I understand the Arria V and 10 Display Port IP core is different and the bug report I mentioned earlier is not relevant for our problem. (please confirm)

    Regarding your suggestion to migrate to a new version of Quartos - our Display port core was bought from Bitech (which was later bought by Altera) and is not supported above Quartos 16.0.

    We tried to compile on Quartos 20.1 the reference design of current display port core but could not get an evaluation *.sof file. If migrating will solve the issue we will be happy to purchase a license or maintenance.

    the lock signal I mentioned earlier is the output of the Arria V Transceiver Native PHY. The setting of this core has a PPM detector threshold that is set to 1000 PPM (similar to reference design) while our reference clock Oscillator is +/- 20PPM (see attached spec). I figure high value on the PPM detector makes the design more robust?

    Our video resolution BW is already 1.62G and the signal looks good on debug monitor while it is locked, however the reference clock seems a bit noisy when we probe it with a deferential probe (see attached image). do you recommend to add "Input Termination" at "OCT 100 Ohms" in the assignment editor? Our differential ref clock pin is currently set to I/O Standard LVDS. Please see clk ref schematics image attached below, the right side nets "DP REF CLK+" and "DP REF CLK-" are connected directly to the Arria V FPGA.

    We tried to check the reference design for dumping the MSA log but it is not clear how to apply it (Please send link or more info on this issue)

    Thanks

    Ariel