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I can see that if a data trace has an unusual delay relative to the other traces on the bus that you could compensate by hard-coding the IOE for that trace with a different delay relative to the others. But what if we made 20 boards and wanted to use the same FPGA design on each board? What if different boards had different delay characteristics on the data bus? I guess Altera is assuming the quality of the boards would be consistent enough and the data eyes on the bus would be wide enough that there would be enough error margin to handle any PVT variations from one board to another. I guess.
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This is the typical use-case, i.e., you use TimeQuest to assign timing constraints, and then the IOE programmable delays are programmed appropriately.
Since you comment on having had this ability with Xilinx devices; did you ever actually need to use them?
I cannot think of a single case where I have needed to adjust the delay to a specific trace. Typically I will get timing constraints for a design working, then based on the operating frequency of the interface, decide if the PCB layout needs to match traces, and then route the board as appropriate.
In todays FPGAs, the fastest interfaces are the transceiver channels, and other than matching differential pairs, there is no need to match trace lengths across lanes.
A more useful question to pose to this group might be; what FPGA interfaces are you interested in, and at what frequencies, eg., DDR3, QDR II+, etc. Most of these interfaces are implemented on Altera development kits, so users of those kits provide feedback on their experiences.
Cheers,
Dave
Honored Contributor
