Are Stratix V IOE delays programmable dynamically?

At this point it’s just an observation I made that it doesn’t look like the delays are dynamically programmable, I mean in the sense of being programmable from logic in the fabric, as I knew I could do with the Virtex-5. It’s not a problem yet. I was just hoping someone would confirm the observation. I’m on an Alera learning curve after using Xilinx for a while.

Dave - It’s interesting to know I might be able to change the settings through JTAG if I need to. Thank you.

Pete – I think I see what you’re saying about changing the relative phase of the internal clock and external clock to get the sampling point right. That could work if all data bus traces are equalized. I wonder about cases where that assumption can’t be made.

I can see that if a data trace has an unusual delay relative to the other traces on the bus that you could compensate by hard-coding the IOE for that trace with a different delay relative to the others. But what if we made 20 boards and wanted to use the same FPGA design on each board? What if different boards had different delay characteristics on the data bus? I guess Altera is assuming the quality of the boards would be consistent enough and the data eyes on the bus would be wide enough that there would be enough error margin to handle any PVT variations from one board to another. I guess.