Are outputs of PLL related all the time?

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1)What if the output frequency is multiple of the input frequency ?

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the slow clock will always align edge with fast clock(in sync) as long as they are phase aligned

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2)What if the output frequency is NOT multiple of the input frequency

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slow clock cannot align at every edge (Out of sync)

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3)What if the output frequency is phase shifted of the input frequency

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never edge aligned but fixed relation(related but not in sync)

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4)What if the output frequency is phase shifted and multiple/non-multiple of the input frequency

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never edge aligned(related but not in sync) / neither