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Altera_Forum's avatar
Altera_Forum
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14 years ago

Are outputs of PLL related all the time?

Hi, Currently, i am timing constraining my FPGA design. I would like to know are the outputs of PLL related with each other (sync) all the time? 1)What if the output frequency is multiple...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks for your reply. so now i know "unrelate" a related clock will not harm.

Could you also answer my previous 4 questions? it will be used for my reference, as to whether to relate or not to relate.

To my understanding, related clocks basically means "In Sync", so output of pll producing the multiple of input frequency are still consider "In Sync", but if it has been phase shifted, means they are "NOT in Sync".

Am i right?