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Altera_Forum
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14 years ago

Are outputs of PLL related all the time?

Hi, Currently, i am timing constraining my FPGA design. I would like to know are the outputs of PLL related with each other (sync) all the time? 1)What if the output frequency is multiple...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Basically you want to know how to determine if two clocks are

related or not so that you decide if their domain needs bridge or not.

The rule of thumb is this: if in doubt treat them as unrelated.

If two clocks are always related to each other in a fixed predictable pattern then you may manage without a bridge.

So you can draw out your waveforms and see effect of frequency and phase.