Are divided clocks synchronous with the source clock?

Thanks JonWay_C. I think that despite the many voices out there saying that a (synchronously) divided clock is synchronous with its source, that it is not in a strict sense because of the variation in the Tco parameter. What I was seeing was hold time violations on data from the divided clock domains going to the source clock domain. This sort of makes sense when you look at the edge of the divided clock being one Tco behind the source, and then the data from the divided domain being one Tco behind the divided clock edge. - providing 2*Tco_max < Th_min. Weird that the EPM family datasheet says that hold time is 0 though.

I was able to fix the violations by using the negative edge of the source clock to clock data from the divided domains. The positive edges of the divided clocks were one Tco behind the positive edge of the source clock and the source clock is very slow (T = 542ns), so there should now be ~270ns of setup and hold time for the data from the divided domains.

Now I get a warning about that I shouldn't be using both edges of the source clock:

(Medium) Rule C106: Clock signal source should not drive registers triggered by different clock edges. Found 1 node(s) related to this rule.
Warning (308010): Node "cpld_master_clock"

Is this really something I should worry about?